1) Field of the Invention
The present invention relates to a selector circuit that receives a plurality of input signals and outputs a single output signal, and more particularly, to a selector circuit that can suppress increase in a wiring area, slowing off of a signal waveform, and a delay of signal transfer.
2) Description of the Related Art
Conventionally, selector circuits are widely used in various information processing devices. A selector circuit is a circuit that selects and outputs only one input signal from among a plurality of input signals.
FIG. 7 is a circuit diagram of an example of a conventional selector circuit. FIG. 7 is an example of the selector circuit that selects and outputs one input signal from among four input signals A to D. In the selector circuit, inverter circuits 1a to 1d invert the signal levels of the input signals A to D, and the input signals with the inverted signal levels become the input signals of pass transistor circuits 2a to 2d. 
Further, the pass transistor circuits 2a to 2d control conduction of the input signals received from the inverter circuits 1a to 1d according to control signals SELA to SELD and XSELA to XSELD.
The signal levels of the control signal SELA and the control signal XSELA are mutually inverted. To be specific, when the signal level of the control signal SELA is “H” (High), the signal level of the control signal XSELA becomes “L” (Low). Conversely, when the signal level of the control signal SELA is “L”, the signal level of the control signal XSELA becomes “H”.
Similarly, the signal levels of the control signal SELB and the control signal XSELB, the signal levels of the control signal SELC and the control signal XSELC, and the signal levels of the control signal SELD and the control signal XSELD are also mutually inverted.
Further, among the control signals XSELA to XSELD, only one signal is set to a different signal level than the rest of the control signals XSELA to XSELD. For example, when the signal level of the control signal XSELA is “L”, the signal level of the control signals XSELB to XSELD becomes “H”.
The pass transistor circuits 2a to 2d conduct the signals when the signal level of the control signals XSELA to XSELD is “L”, and block the signals when the signal level of the control signals XSELA to XSELD is “H”.
As a result, among the signals that are output from the inverter circuits 1a to 1d, only one signal is input into an inverter circuit 3 via a wire 4, and an output signal X with an inverted signal level is output.
The inverter circuits 1a to 1d and the inverter circuit 3 are provided in a selector circuit shown in FIG. 8 in order to stabilize the signal potential of the input signals A to D and the output signal X.
FIG. 8 is a circuit diagram of a control-signal generating circuit that generates control signals SELA to SELD and XSELA to XSELD input into pass transistor circuits 2a to 2d shown in FIG. 7.
In the control-signal generating circuit shown in FIG. 8, pairs of control signals with mutually inverted signal levels can be generated according to the combination of the input signals I and J. In other words, pairs of the control signals SELA and XSELA, the control signals SELB and XSELB, the control signals SELC and XSELC, and the control signals SELD and XSELD can be generated. Moreover, from among the control signals XSELA to XSELD, only one signal can be set to a different signal level than the rest of the control signals XSELA to XSELD. FIG. 9 is a table of signal levels of the signals that are generated by the control-signal generating circuit shown in FIG. 8.
In the selector circuit in FIG. 7, when the distance between the pass transistor circuits 2a to 2d and the inverter circuit 3 is large, the wiring area can be reduced by integrating four wires into a single one and extending the integrated wire. However, this increases the load capacitance of the wire 4, thus causing slowing of the waveforms of the input signals that are input in the inverter circuit 3, resulting in signaling delay.
Forming a plurality of signal input systems and designing circuits in a way so that a plurality of output signals from these signal input systems are received in a multi-input CMOS logic circuit can overcome this drawback, as disclosed in Japanese Patent Laid-Open Publication No. H9-93118.
FIG. 10 is a circuit diagram of a conventional pass transistor logic circuit disclosed in Japanese Patent Laid-Open Publication No. H9-93118. In the pass transistor logic circuit, a pass transistor circuit 10a and a pass transistor circuit 10b form a first signal input system. A pass transistor circuit 10c and a pass transistor circuit 10d form a second signal input system.
Output signals from the first and the second signal input systems, are input into a NAND circuit 11 via two wires. Thus, by inputting the output signals from the first and the second signal input system into the NAND circuit 11 to separate wires, the load capacitance of the wires can be reduced, thereby remedying slowing of signal waveforms and signaling delay.
Moreover, in the circuit in FIG. 10, since even extending the wire can reduce the load capacitance of the wire, the pass transistor circuits 10a to 10d can be provided at a distance from the NAND circuit 11 when it is not possible to secure a wiring area around the NAND circuit 11.
In this case, the wiring area of the NAND circuit 11 with the pass transistor circuits 10a to 10d is substantially similar to that the wiring area shown in FIG. 7. Thus, the increase in the wiring area can be prevented.
FIG. 11 is a detailed circuit diagram of the conventional pass transistor logic circuit disclosed in Japanese Patent Laid-Open Publication No. H9-93118. In the pass transistor logic circuit, a pass transistor circuit 12a and a pass transistor circuit 12b form a first signal input system. A pass transistor circuit 12c and a pass transistor circuit 12d form a second signal input system.
A NAND circuit is formed with p-channel MOS transistors 13a and 13b and n-channel MOS transistors 13c and 13d. Moreover, in the pass transistor logic circuit, p-channel MOS transistors 14a, and 14b, stabilize the signal levels of signal X and signal Y with the aid of output signal Z of the NAND circuit.
However, the circuitry in the conventional technology disclosed in Japanese Patent Laid-Open Publication No. H9-93118 does not form the selector circuit that outputs one signal selected from a plurality of input signals.
In other words, structure of the selector circuit that can prevent increase in the wiring area, slowing of the signal waveforms and signaling delay goes beyond providing a plurality of signal input systems requiring a device for generating the control signals for the pass transistor circuits 10a to 10d and 12a to 12d that control the conduction of signals.